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AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
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C Compiler for AVR32 Microprocesor
Nagy, Michal ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This bachelor's thesis deals with creation of an AVR32 backend for the LLVM compiler framework. The core of this work consists of explaining the way of architecture description in LLVM and of my own implementation of the AVR32 backend. Furthermore, several problems encountered during the implementation are discussed along with their possible solutions. As the result of this work functional backend, with a few constraints discussed in the conclusion chapter, was created.
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Finding the network architecture for alarm transmission system LAN-RING
Mikšíček, Pavel ; Marada, Tomáš (referee) ; Zuth, Daniel (advisor)
This master’s thesis deals with a complex solution for the visualization of network topology. The first part of thesis describes the operation principle of LLDP protocol, which was chosen as a tool for retrieving informations from network traffic based on the requirement of the assignment. There is a detailed description of the LLDP protocol implementation in C language to METEL s.r.o. network products. The second part deals with possibilities of graphical interface in software SIMULand intended for managing network devices. It describes tools expansion process for the visualization of the network topology. In conclusion, the results of testing final solution are introduced.
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Sound Module for Evaluation Kit
Priškin, Jiří ; Číž, Radim (referee) ; Sysel, Petr (advisor)
This thesis is dealing with design and putting into operation of sound module for evaluation kit Atmel ATSTK1000. At the beginning, there is an introduction with properties, hardware and software equipment of the evaluation kit which is used for development of embedded devices based on AT32AP7000. The microcontroller AP7000 is a complete system on chip with an AVR32 microprocessor core, containing additional supporting circuits, controllers and interfaces which the core itself does not have included. However, there is no digital to analog converter for audio signal processing. This has led to design an additional module performing this task. A part of thesis describes Intel AC‘97 standard including AC-link interface, which is used for full-duplex data transmission between realized sound module and the evaluation kit STK1000. The sound module is designed as a plug-in card. The last chapter presents the Linux operating system installation process as an SD/MMC Flash memory card boot image creation and test of the sound module under ALSA architecture.
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AVR32 Model Coreation
Sarčák, Rostislav ; Kajan, Michal (referee) ; Masařík, Karel (advisor)
This barchelor's thesis describe creation of AVR32 processor instruction-accurate model using CodAL language. In this thesis RISC AVR32 architecture, approach to implementation of the model, testing and generating of software toolchain is described. Model development is realized in Codasip framework. Model contains implementation of AVR32 instruction set. The result of this work is AVR32 processor instruction-accurate model.
|
|
|
C Compiler for AVR32 Microprocesor
Nagy, Michal ; Husár, Adam (referee) ; Hruška, Tomáš (advisor)
This bachelor's thesis deals with creation of an AVR32 backend for the LLVM compiler framework. The core of this work consists of explaining the way of architecture description in LLVM and of my own implementation of the AVR32 backend. Furthermore, several problems encountered during the implementation are discussed along with their possible solutions. As the result of this work functional backend, with a few constraints discussed in the conclusion chapter, was created.
|
|
|
Finding the network architecture for alarm transmission system LAN-RING
Mikšíček, Pavel ; Marada, Tomáš (referee) ; Zuth, Daniel (advisor)
This master’s thesis deals with a complex solution for the visualization of network topology. The first part of thesis describes the operation principle of LLDP protocol, which was chosen as a tool for retrieving informations from network traffic based on the requirement of the assignment. There is a detailed description of the LLDP protocol implementation in C language to METEL s.r.o. network products. The second part deals with possibilities of graphical interface in software SIMULand intended for managing network devices. It describes tools expansion process for the visualization of the network topology. In conclusion, the results of testing final solution are introduced.
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|
| |
|
|
Sound Module for Evaluation Kit
Priškin, Jiří ; Číž, Radim (referee) ; Sysel, Petr (advisor)
This thesis is dealing with design and putting into operation of sound module for evaluation kit Atmel ATSTK1000. At the beginning, there is an introduction with properties, hardware and software equipment of the evaluation kit which is used for development of embedded devices based on AT32AP7000. The microcontroller AP7000 is a complete system on chip with an AVR32 microprocessor core, containing additional supporting circuits, controllers and interfaces which the core itself does not have included. However, there is no digital to analog converter for audio signal processing. This has led to design an additional module performing this task. A part of thesis describes Intel AC‘97 standard including AC-link interface, which is used for full-duplex data transmission between realized sound module and the evaluation kit STK1000. The sound module is designed as a plug-in card. The last chapter presents the Linux operating system installation process as an SD/MMC Flash memory card boot image creation and test of the sound module under ALSA architecture.
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